1. Field of the Invention
The present invention relates to a CAD (Computer Aided Design) system to support designing hardware, and, more particularly, to a design support system with an improved input support function for hardware synthesis system, which runs an operation based on a hardware description input.
2. Description of the Related Art
As the scale of digital systems becomes larger, various CAD systems have been developed to improve the design efficiency to accomplish circuit designs and/or achieve LSI of a designed circuit.
In particular, recently, simulators for validating the functions of hardware to be designed (hereinafter simply referred to as "target hardware"), based on the input functional specification of that hardware, which is described with a hardware description language having a syntax similar to a software programming language, not information on the connection of target circuits, and systems for automatically generating logical circuits (hereinafter called "logic synthesis systems") have been put into practice as systems for supporting the circuit design from the functional design phase.
The "hardware description language" is a language from which a circuit can automatically be generated having functions which match input conditions that are the specifications of inputs, outputs, functions, bit structures, etc. described in a program fashion. Further, it is possible to accomplish mask design for achieving LSI circuits as well as design circuits that realize the intended functions can be designed by processing a hardware description language by a hardware synthesis system.
Designers design intended digital circuits in the following process using a design support system, such as 10 the aforementioned CAD system or logic synthesis system:
(1) First stage: Describe the functional specification of target hardware using a hardware description language. PA1 (2) Second stage: validate the description of the functional specification attained in the first stage using a simulator. PA1 (3) Third stage: Automatically generate a logical circuit by a logic synthesis system using the description of the functional specification which has been examined by the simulator in the second stage. PA1 (1) Logic synthesis system is suited to mainly generate random logic circuit for a control logic, and circuits of a data path, such as arithmetic operational 10 units and memory, can be designed efficiently and to have higher operational speeds if designed manually or a module generator specially designed for those units. PA1 (2) The processing performance of a logic synthesis system is limited, i.e., there is a certain range for the amount of the description in which or the reasonable circuit can be synthesized, or the circuit can be synthesized in the reasonable processing time. PA1 indication means for indicating one of a first mode inputting an information to specify the second functional elements and a second mode inputting an information to specify the first functional elements; PA1 interface signal generating means for executing one of a first operation which acquires input/output elements from the first functional elements associated with the second functional elements according to the first mode and generates all necessary interface signal information to be exchanged between the first functional element block and the second functional element block, based on the input/output elements and information of the second functional elements, and a second operation which acquires input/output elements from the first functional elements associated with the first functional elements according to the second mode and generates all necessary interface signal information to be exchanged between the second functional element block and the first functional element block, based on the input/output elements and information of the first functional elements; and PA1 functional specification dividing means for replacing a description of the second functional elements described in the functional specification to a description using the interface signal information generated by the interface signal generating means to produce a functional specification of the first functional element block. PA1 a first step of acquiring one of a first input/output elements associated with the second functional elements and a second input/output elements associated with the first functional elements; PA1 a second step of executing one of a first operation which generates all necessary interface signal information to be exchanged between the first functional element block and the second functional element block, based on the first input/output elements and information of the second functional elements, and a second operation which generates all necessary interface signal information to be exchanged between the second functional element block and the first functional element block, based on the second input/output elements and information of the first functional elements; and PA1 a third step of excluding the functional specification of the second functional elements from the general functional specification and receiving the interface signal information generated to produce a functional specification of at least one of the first functional element block and the second functional element block.
If what should be input to the logic synthesis system to automatically generate a logical circuit is the whole description of the functional specification written in the first stage, the description in the first stage can be the same as that in the third stage. However, the description of the functional specification in the third stage becomes slightly different from that in the first stage because of the use of the logic synthesis system in the third stage. More specifically, the description for validating the functions in the first stage often differs from the description for logic synthesis in the third stage due to the following reasons.
Particularly, since the primary objective of the description in the first stage is to check the function of the overall design target, the description is often written for each large functional block without being conscious of detailed circuit block structures in the logic design.
In dividing the target circuit into blocks, it is necessary to find out all the interface signals between the divided blocks, or all the signal lines through which signals should interface between the divided blocks. The finer the block division becomes, therefore, the more complicated this task becomes. As reference to those interface signals and a description for assigning values to these signals become necessary, the amount of the description of the specifications and the work to provide the description increase. Apparently, this does not meet the objective of the functional validation to "quickly check the basic operations of the whole target circuit based on a abstract specification description (model)". In addition, when the divided blocks become too small, it is difficult to prepare significant (probable) test data for each block.
In view of the above, the following scheme is employed.
First, some of small functional blocks to acquire the intended circuit are treated as a large functional block and a specification for each such large functional block is described. The functions are checked for the specification description of each large functional block as well as the functions of the whole circuit are checked. Then, the specification descriptions of the large functional blocks are manually sorted into blocks which are to be manually designed and those which are to be subjected to logic synthesis in consideration of logic design elements, such as the data path section, control section, logic synthesis section and manually designing section.
Next, the descriptions of the functional specifications of those blocks which belong to the logic synthesis group are also prepared manually. The functional descriptions for validation are manually rewritten into the functional specification descriptions for divided blocks for the logic synthesis group using an editor or the like in the above manner.
Because the functional specifications of a design target are often described twice during the design process as explained above, this design scheme is a bottle-neck in designing an intended circuit using a high level CAD system. The troublesome task of finding out all the interface signals between blocks should also be considered, as described earlier.
In short, in a digital circuit design using the language of describing the functional specification of hardware, a simulator and a logic synthesis system, normally, the functional specification description for checking the general operation (functional specification description for functional validation) should be prepared and simulated, then, the functional specification description for a logic synthesis group, which is the functional specification description for a manual design group excluded from the validated functional specification description, should be prepared again and be subjected to logic synthesis by the logic synthesis system.
The conventional scheme of designing a target circuit, therefore, involves the description of the functional specification for the functional validation and that for the logic synthesis, complicating the overall work. Further, when the functional specification description for logic synthesis is prepared, this description should be validated by a simulator before accomplishing the logic synthesis, resulting in lower productivity.